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When

Oct. 9, 2026, 10 a.m.
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Friday, October 9, 2026, 10:00 a.m.

Kemal Aygün
IEEE Fellow

"High-Speed Chiplet Interconnects: Packaging Technologies, Modeling and Scaling"

ECE 530 | Zoom link

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Abstract:
With the rapid growth of artificial intelligence (AI), high-performance computing, and data-centric applications, future electronic systems face unprecedented performance and bandwidth demands. A key enabler for continued scaling is advanced system-in-package integration, where heterogenous dies and chiplets are interconnected through dense, high-bandwidth interconnect architectures. This drive toward ultra-high bandwidth, lower energy per bit, and reduced latency in AI workloads is accelerating developments in both electrical signaling and emerging co-packaged optics (CPO), requiring novel integration constructs, advanced materials, associated modeling, simulation and metrologies.

This presentation reviews recent advances and foundational concepts in electronic packaging for high-speed electrical and emerging optical (CPO) interconnects. Topics include 2D, 2.5D, and 3D integration architectures, physical-layer signal integrity challenges and electromagnetic modeling and characterization methodologies. The talk also highlights current die-to-die interface standards, fundamental trade-offs and open research challenges in heterogenous integration.

Bio:
Kemal Aygün is an IEEE Fellow and former Intel Fellow with 20+ years of technical leadership in high-speed signaling, computational electromagnetics, advanced semiconductor packaging and heterogenous integration. He directed and led Intel's corporate high-speed signaling roadmaps and external research consortia to support and deploy breakthrough packaging, assembly and system-level signaling technologies. This included enabling Intel's Embedded Multi-Die Interconnect Bridge (EMIB), open standards such as Universal Chiplet Interconnect Express (UCIe) and the development of emerging co-packaged optics (CPO) C 224G/448G serializer/deserializer (SerDes) architectures. He served as General Chair of the 2020 IEEE Electronics Packaging Society. He graduated with a PhD in electrical and computer engineering from the University of Illinois Urbana-Champaign.